Complementary metal oxide semiconductor (CMOS) technology is the prevalent technology employed for manufacturing ultra large-scale integrated (ULSI) circuits. In general, the CMOS technology desirably employs silicon wafers having a crystal orientation of (100). This crystal orientation is selected for its low surface state density and high electron mobility in the (100) plane. In this regard, an n-channel transistor formed on a silicon substrate with a crystal orientation of (100) provides a large and desirable source-to-drain current.
In contrast, silicon substrates having a crystal orientation of (110) are known to maximize hole mobility in chip transistors. Thus, although crystal orientations (100) optimize electron mobility, this optimized bulk crystalline (100) behavior correspondingly limits hole mobility for transistors on the chip, ultimately sacrificing an overall dynamic performance of the CMOS chips.
In sub-250 nm CMOS technologies, the use of silicon-on-insulator (SOI) substrates is desirable in order to obtain low junction capacitances and high device speed. However, current CMOS technologies employing (100) orientation silicon-on-insulator wafers can limit the overall dynamic performance of the device, as described above. Therefore, a need exists to optimize the performance of nFET and pFET transistors on SOI-based chips.
For these and other reasons, there is a need for the present invention.